
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY zero_x0 IS
PORT(
  nq	: OUT STD_LOGIC
);
END zero_x0;

ARCHITECTURE RTL OF zero_x0 IS
BEGIN
  nq <= '0';
END RTL;
